A HALF-MICRON CMOS LOGIC GENERATION

During the early 1990s, half-micron lithography was demonstrated in 16 Mb DRAM fabrication. Utilization of this capability for CMOS logic dev ices within IBM followed with a trio of programs, each with different performance, density, feature list, and schedule. The first version me lded 3.3/3.6-V 16Mb DRAM MOSFET devices with an improved version of an existing dense, planar, reliable multilevel backend-of-line (BEOL) me tallization and wiring technology. Since it was built directly from ex isting technologies, it was released quite quickly. A 3.3-V follow-on technology was added several months later. This logic offering added a local interconnect and a faster device. A second follow-on achieved g reater speed improvement, calling upon a 2.5-V power supply and very t ight channel-length control to obtain performances 50% above previous- generation standards, at lower power.