STATIC BARRIER MIMD - ARCHITECTURE AND PERFORMANCE ANALYSIS

In this paper, we describe and analyze the performance of a new archit ectural construct - an efficient synchronization mechanism called ''St atic Barrier MIMD'' or SBM. Unlike traditional barrier synchronization , the proposed barriers are designed to allow static (compile-time) co de scheduling to eliminate some synchronizations. The static barrier M IMD hardware is more general than most hardware barrier mechanisms, al lowing any subset of the processors to participate in each barrier. Th e barriers execute in a small number of clock ticks, and processors pr oceed simultaneously past the barrier. The performance of idealized ba rrier schedules is examined to gain insights into code scheduling for barrier MIMD machines. (C) 1995 Academic Press, Inc.