TEST SYNTHESIS FROM BEHAVIORAL DESCRIPTION BASED ON DATA TRANSFER ANALYSIS

We developed a new test-synthesis that operates method based on data t ransfer analysis at the language level. Using this method, an efficien t scan path is inserted to generate test data for the sequential circu it by using only a test generation tool for the combinatorial circuit. We have applied this method successfully to the behavior, logic, and test design of a 32-bit, RISC-type processor. The size of the synthesi zed circuit without test synthesis is 23,407 gates; the size with test synthesis is 24,811 gates. This is an increase of only a little over 6%.