0.15 MU-M CMOS DEVICES WITH REDUCED JUNCTION CAPACITANCE

0.15 mu m CMOS transistors have been fabricated. TiSi2 salicide was us ed for the gate electrode and source/drain to reduce parasitic resista nce. Electron beam (EB) lithography was used for the gate patterning. Since the channel impurity was implanted only around the gate to reduc e the junction capacitance, a reasonably short ring oscillator delay o f 33 ps was obtained at 1.9 V supply voltage. The parasitic resistance and capacitance contribution to the delay time was analyzed by SPICE simulation. It was shown that the localized channel implant is effecti ve for scaling the delay time and power consumption, because the sourc e/drain size is difficult to scale down to as small as the gate length .