FABRICATION AND DELAY-TIME ANALYSIS OF DEEP-SUBMICRON CMOS DEVICES

This paper describes the fabrication of 0.1 mu m gate length CMOS devi ces and analysis of delay time by circuit simulation. In order to redu ce the gate resistance, TiN capped cobalt salicide technology is appli ed to the fabrication of 0.1 mu m CMOS devices. Gate sheet resistance with a 0.1 mu m gale is as low as 5 Omega/sq. Propagation delay times of 0.1 mu m and 0.15 mu m CMOS inverter are 21 ps and 36 ps. Simulated propagation delay time agreed fairly well with experimental results. For gate length over 0.15 mu m, intrinsic delay in CMOS devices is the main delay factor. This suggests that increasing current drivability is the most efficient way to improve propagation delay time. At 0.1 mu m, each parasitic component and intrinsic delay have similar contribu tions on device speed due to the short channel effect. To improve dela y time, we used rapid thermal annealing or a high dose LDD structure. With this structure, drain current increases by more than 1.3 times an d simulation predicted a delay time of 28 ps is possible with 0.15 mu m CMOS inverters.