HARDWARE DESIGN AND VLSI IMPLEMENTATION OF A BYTE-WISE CRC GENERATOR CHIP

In this paper the hardware design and VLSI implementation of a byte-wi se CRC generator is presented. The algorithm is based on the work pres ented in in which a software implementation was proposed. The byte-wis e CRC algorithm is translated to hardware and expressed in AHPL. The m ethod used here calculates CRC 'on the fly' and is much faster than th e look-up table method proposed by Lee. The chip is 8 times faster tha n the serial implementation of with smaller hardware requirements (occ upies lesser area). The number of clock cycles required to generate an d transmit any CRC (for an 8 byte message) is just two more than the t ime required to calculate it (in all 10 clock pulses). The CRC chip ca n be used in a number of applications. These include areas such as err or detection and correction in data communications, signature analysis , and mass storage devices for parallel information transfers.