AUTOMATED VHDL COMPOSITION FROM AHPL

Hardware description languages (HDLs) have been widely used for docume ntation, communication, and verification. They have also been used as input specification languages to Design Automation (DA) systems which synthesize VLSI layouts. AHPL is an HDL that has been in use for the p ast two decades in modeling digital systems. Recently a language calle d VHDL (VHSIC Hardware Description Language) developed under the auspi ces of the United States Department of Defense Very High Speed Integra ted Circuits Program, is rapidly emerging as the next generation Desig n Automation Language. In this paper, we present a tool for the automa tic composition of VHDL descriptions from their equivalent AHPL specif ications. Central to the composition algorithm is a template which is the skeleton of a generic VHDL model consisting of a small subset of V HDL constructs that are sufficient to capture VHDL equivalent descript ions of any input AHPL model. The Composer will be illustrated with th e help of an example.