PARTIAL SCAN DESIGN BASED ON SIMULATED ANNEALING FOR HARD-TO-DETECT FAULTS

In this paper, we describe algorithms based on Simulated Annealing for selecting a subset of flip-flops to be connected into a scan path. Th e objective for selection is to maximize the coverage of faults that a re aborted by a sequential fault simulator. We pose the problem as a c ombinatorial optimization, and present a heuristic algorithm based on Simulated Annealing. The SCOAP testability measure is employed to asse ss the selection of flip-flops during the course of optimization. Our algorithms form a part of an integrated design package, TOPS, which ha s been designed as an enhancement to the OASIS standard-cell design au tomation system available from MCNC [1]. We discuss the TOPS package a nd its performance on a number of ISCAS'89 benchmarks. We also present a comparative evaluation of the circuit benchmarks.