ASSEMBLY-LEVEL RELIABILITY - A METHODOLOGY FOR EFFECTIVE MANUFACTURING OF IC PACKAGES

This paper discusses the general methodology of assembly level reliabi lity (ALR) as part of a corporate effort at designing reliability into the whole assembly process of integrated circuit (IC) packages. Semic onductor packages with assembly-induced defects sometimes do escape de tection due to a variety of reasons. Trying to eliminate this problem by approaching it piecemeal may result only in single process optimiza tion, but does not guarantee full assembly line balancing for error-fr ee production. ALR is a systematic 4-prong approach which uses a combi nation of techniques for synergistic effects. 1) Problems of immediate needs have to be addressed and contained, 2) The proper steps must th en be taken to ensure that similar issues do not resurface. 3) Design- for-manufacturability principles must be applied; eg, the design of th e package can be simplified to reduce the number of assembly steps, in crease throughput, and cut cost. 4) Qualification methodologies have t o be revisited. Less expensive but well-characterized test chips can b e introduced in lieu of actual devices. Accelerated testing with a goo d understanding of the failure mechanisms facilitates faster product q ualification to ensure time-to-market advantage. Together with these m ore cost-effective qualification techniques, the proper reliability-mo nitoring features must be installed. Only then can the true vision of ALR be accomplished, viz, ensuring recognition, by both customers and competitors, as a Company that continuously manufactures defect-free p arts.