EXPERIMENTAL INVESTIGATION OF AN ADVANCED STATIC VAR COMPENSATOR

An advanced static VAr compensator (ASVC) employing a three-level inve rter is presented. The paper describes the operating principles and co nstruction of a hardware model of this ASVC scheme. The performance of the ASVC is obtained from an experimental study carried out on the la boratory model. The use of the selective harmonic elimination modulati on technique (SHEM) to minimise harmonics is explored. Experimental st udies have been carried out to determine the effect of the DC-side cap acitor on the harmonic performance of the scheme and the open-loop res ponse speed is also evaluated. Finally, the economic feasibility of th is scheme is briefly assessed by comparing the GSVC with a conventiona l thyristor-controlled reactor/fixed-capacitor scheme.