VLSI DESIGN OF OPTIMIZATION AND IMAGE-PROCESSING CELLULAR NEURAL NETWORKS

Detailed design of a current-mode cellular neural network for optimiza tion and image processing is presented, The hardware annealing functio n is also embedded in the network, It is a paralleled version of fast mean-held annealing in analog networks, and is highly efficient in fin ding globally optimal solutions for cellular neural networks. The netw ork was designed to perform programmable functions for fine-grained pr ocessing with annealing control to enhance the output quality. A 5 x 5 prototype chip was fabricated in a 2.0 mu m CMOS technology. Since th e MOSIS scalable design rules are used, it is also suitable for submic ron technologies, For high circuit reliability and compactness purpose : a unit current of 6.0 mu A is used, The cell density is 505 cell/cm( 2) and the cell time constant is chosen to be 0.3 mu s. From this prot otype, a scalable VLSI core of around 50 x 50 neural processors can be integrated on a 1-cm(2) silicon area in a 0.8 mu m technology, Experi mental results of building blocks and the prototype chip are also pres ented.