MULTIPLE-VALUED LOGIC MEMORY CIRCUIT

A new voltage-mode CMOS multiple-valued logic (MVL) memory circuit has been realized in a standard 2 mu m p-well polysilicon-gate CMOS techn ology. This circuit requantizes MVL voltages during a setup clock mode and latches the input value during the hold clock mode. Using a 5V su pply and logical voltage increments of 1.67 V, a quaternary memory cir cuit with a worst-case total setup and hold time of about 7 ns, and a best single-level transition total setup and hold time of about 1 ns h as been realized.