DEVELOPMENT OF LOW OPERATING VOLTAGE 64-MBIT DRAM

The authors have developed the commercial product of low-power and hig h-speed 64 Mbit DRAMs, of which x 4, x 8 and x 16 bit I/O organization s are available in the same package by Lead On Chip (LOC) technology. The product is commercially available as a 3.3+/-0.3 V supply voltage DRAM, performs an access time (t(RAC)) of 38 ns (at V-CC = 3.0 V, T-a = 70 degrees C); with an active current (I-CC1) of 56 mA in the x 8 bi t I/O with 8,192 refresh cycle mode (at V-CC = 3.6 V, t(RC) = 130 ns), utilizing a triple well and an internal boosted voltage generator. Co st increase factors have been cut through the selection of a divided w ord decoder scheme with main and sub word-lines. This paper describes method, circuit, device and process technologies used in this DRAMs.