SYNTHESIS TECHNIQUES FOR LOW-POWER DIGITAL DESIGNS

The increasing demand for ''portable'' computing and communication, ha s imposed power consumption to be one of the most influential design p arameters. Since 1991, the VLSI CAD group of NEC USA at Princeton has been developing design methodologies and CAD tools for power minimizat ion. This paper surveys authors' system of design methodologies and CA D tools for power minimization at logic, behavioral and system levels. The effectiveness of methodologies and tools is demonstrated on a var iety of examples.