ARQ PROTOCOLS FOR HIGH-SPEED HARDWARE IMPLEMENTATION

In order to fully exploit high speed communication channels the proces sing burden at the end points must be reduced. One way in which this c an be done is by shifting the implementation of protocols from softwar e to specialized, dedicated hardware. This process is made easier if t he protocols are designed with hardware implementation in mind. In thi s paper we consider a family of ARQ protocols that can be implemented through relatively simple hardware-one or more FIFO buffers and some l imited state information. With a single FIFO buffer the protocol is id entical to a regular Go-Back-N. By increasing the number of FIFO buffe rs we can reach a full selective repeat. The main result is to show th at, for typical error rates, performance close to selective repeat can be obtained with two or three FIFO buffers. The family of protocols i s described in detail followed by throughput analysis. For the two buf fer case a closed-form solution is obtained while for other cases simu lation results are given.