MANIFESTATIONS OF FAULTS IN SINGLE-BJT AND DOUBLE-BJT BICMOS LOGIC GATES

Combining the inherent advantages of bipolar and CMOS, BiCMOS is emerg ing as a major technology for high-speed, high-performance, digital an d mixed-signal applications. Logic behaviour of single- and double-BJT BiCMOS devices under transistor-level shorts and opens is examined. I n addition to sequential behaviour, some stuck-open faults exhibit inc reased delay. While most stuck-on faults can be detected by logic leve l testing, some of them can only be detected by monitoring the power s upply current (I(DDQ) monitoring). A stuck-open fault in double-BJT Bi CMOS device manifesting as enhanced dynamic I(DD) current is shown. Th e faulty behaviour of bipolar (TTL) and CMOS logic families is compare d with BiCMOS. Testability of both single- and double-BJT BiCMOS devic es are discussed along with a design for a testability approach for de tecting stuck-open faults in S-BJT BiCMOS devices.