PERFORMANCE ANALYSIS OF DISTRIBUTED-MEMORY COMPUTERS WITH PARALLEL NODE ARCHITECTURE

In a distributed memory computer (DMC), parallelism at node level can be achieved by use of pipelined arithmetic units or communication proc essors that allow overlap between processing and communication activit ies. We derive a performance model for distributed memory computers wh ose nodes are vector-processing elements (VPEs), i.e., nodes with a pa rallel internal architecture. The model is based on the one introduced by Hockney for SIMD computers and shared-memory MIMD architectures. T he approach has been extended to distributed-memory architectures, inc luding VPE networks, to achieve a powerful characterization of these s ystems in terms of a few performance parameters. The discussion points out how vector capabilities can be effectively exploited in DMCs and identifies the parameters of the concurrent system (hardware and softw are) that most significantly affect the overall performance. Finally, the generality of the model is discussed with respect to different kin ds of VPE architectures proposed in the literature or available on the market.