TESTING VLSI REGULAR ARRAYS

In recent years the concept of 'Design for Test'-whereby the designer is forced to comply with a specific test style-has become very popular . However, the most effective custom VLSI architectures available all have their own very strongly defined structure. Therefore, test strate gies are required which exploit the typical hierarchy in the design. E xploiting this hierarchy implies a test philosophy which requires the minimum addition of extra test logic and utilizes the hierarchy of the design. A popular VLSI architecture is a systolic array which consist s of a regular array of small processing elements with timing latches on the communication lines. In this case we can exploit the regularity for test purposes; in this paper we show how to do this by adopting a divide and conquer method. This can be done by generating test vector s for a single processing element, using the most appropriate fault mo del. The regularity of the array facilitates the propagation of these vectors to every other processing element in the array. The propagatio n method must also allow for the propagation of the fault effects from the output of each processing element to the boundary of the array wh ere the fault can be observed, The proposed test method presented in t his paper takes the vectors required to test a single processing eleme nt, and determines test vectors for the whole array, This method is ap plicable to all types of regular arrays, but in particular, systolic a rrays, where we have the added problem of circuit timing. Each separat e signal direction is first analyzed for its test vector and fault eff ect propagation properties. Then, using the array Data Dependence Grap h, which represents the propagation of data through the array, the com bined effect of all signals on test vector and fault effect propagatio n can be considered. This reduces the task of determining the array in puts to a pattern matching problem suitable for computer implementatio n. The test method is applied to three different arrays to illustrate how different array types can be tested.