A CMOS SERIAL LINK FOR FULLY DUPLEXED DATA COMMUNICATION

This paper describes a CMOS serial link allowing fully duplexed 500 Mb aud serial data communication, The CMOS serial link is a robust and lo w-cost solution to high data rate requirements, A central charge pump PLL for generating multiphase clocks for oversampling is shared by sev eral serial link channels, Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end, The digital PLL accomplishes proce ss-independent data: recovery by using a low-ratio oversampling, a maj ority voting, and a parallel data recovery scheme;. Mostly, digital ap proach could extend its bandwidth further with scaled CMOS technology, A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 mu m CMOS process technology, The test chip conf irms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.