A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 m
u m CMOS technology is described, The PLL supports internal to externa
l clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous st
atic power down modes for PowerPC(TM) microprocessors. The CPU clock l
ock range spans from 6 to 175 MHz, Lock times below 15 mu s, PLL power
dissipation below 10mW as well as phase error and jitter below +/-100
ps have been measured, The total area of the PLL is 0.52 mm(2).