A MULTIPLEXER-BASED ARCHITECTURE FOR HIGH-DENSITY, LOW-POWER GATE ARRAYS

This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells, The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers, The multiplex er can be used to create any 2 input and some 3 input functions in one basecell, Internal fanout, rather than typical output load, defines t he size of driver and multiplexer transistors, which can be independen tly tailored for the desired speed/area/power target, This basecell, w hich is well suited for implementing datapath elements, has been used to create a 16 x 16-b multiplier operating at 50 MHz in 314 500 mu m(2 ) in 0.6 mu m technology.