A 6-NS 4-MB CMOS SRAM WITH OFFSET-VOLTAGE-INSENSITIVE CURRENT SENSE AMPLIFIERS

Authors
ISHIBASHI K TAKASUGI K TOYOSHIMA H YAMANAKA T FUKAMI A HASHIMOTO N OHKI N SHIMIZU A HASHIMOTO T NAGANO T NISHIDA T
Citation
K. Ishibashi et al., A 6-NS 4-MB CMOS SRAM WITH OFFSET-VOLTAGE-INSENSITIVE CURRENT SENSE AMPLIFIERS, IEEE journal of solid-state circuits, 30(4), 1995, pp. 480-486
Citations number
8
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE journal of solid-state circuits → ACNP
ISSN journal
00189200
Volume
30
Issue
4
Year of publication
1995
Pages
480 - 486
Database
ISI
SICI code
0018-9200(1995)30:4<480:A64CSW>2.0.ZU;2-M
Abstract
A 4-Mb CMOS SRAM with 3.84 mu m(2) TFT load cells is fabricated using 0.25-mu m CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V, The use of a current sense amplifier tha t is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells.