A 0.65-NS, 72-KB ECL-CMOS RAM MACRO FOR A 1-MB SRAM

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65- ns address-access time, 0.80-ns write-pulse width, and 30.24-mu m(2) m emory cells has been developed using 0.3-mu m BiCMOS technology, Two k ey techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a repl ica memory cell, These circuit techniques can reduce access time and w rite-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits, In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twiste d bit-line structure with a normally on MOS equalizer is proposed, The se techniques are especially useful for realizing ultrahigh-speed, hig h-density SRAM's, which have been used as cache and control storages i n mainframe computers.