A SOURCE SENSING TECHNIQUE APPLIED TO SRAM CELLS

A new CMOS cell design is proposed, analyzed, and implemented in an AS IC macrocell generator to evaluate the performance and reliability of sensing the ground return current produced in the cell during read acc ess, Both single and dual port cell configurations are studied for sta tic noise margin (SNM), writing requirements, and source offset voltag e effects, To frame the advantages and differences of the SSS cell, a comparison is made to several conventional SRAM cells, Noise margins a re found to be the same or better than conventional cells, and where d esign allows cell device ratio optimizations, single ended access cell s can generate greater SNM than differential cells, The source sensing technique was evaluated by inserting the new cell in a 0.5 mu m ASIC memory block and tested on standard ASIC test sets.