In this paper, we study the net adding problem arising in VLSI layout
process. Given a layout H and a new net N, we attempt to add net N to
layout H without changing H. We present an efficient method to find a
solution or report there is no solution to the given problem. Our solu
tion is optimal in minimizing the number of vias required in two-termi
nal cases, and nearly optimal in multi-terminal cases.