PATH-DELAY-FAULT TESTABLE NONSCAN SEQUENTIAL-CIRCUITS

In this paper we show that any finite state machine can be implemented by a fully path-delay-fault testable nonscan sequential circuit. Synt hesis methods are proposed, which use a one-hot encoding of states, a special circuit structure and at most one additional input. Combined w ith existing synthesis techniques for delay-fault testable combination al circuits, these methods can produce nonscan sequential circuits in which every path has a robust or validatable nonrobust test.