A 5-NS 32-K X8 X9 BI-CMOS TTL SRAM WITH ALTERNATED BIT-LINE LOAD ARCHITECTURE/

An ultrahigh-speed 32 K x8/x9 TTL bi-CMOS SRAM with a 5-ns standard ac cess time was developed using a five-layer polysilicon/two-layer alumi num 0.6-mu m bi-CMOS process with 4.2 x 5.6-mu m(2) 4-M SRAM-class sma ll-size memory cells, ultrahigh capacity, self-aligned bipolar electro des with 18.5-GHz cutoff frequency and 0.6-mu m/0.7-mu m (nMOS/pMOS) g ate-length MOS transistors. This fast access time was achieved by usin g center power pin-out to reduce output noise, a major problem in the TTL SRAM, together with alternated bit line load architecture, a memor y array architecture well suited to center power pin-out. Also used we re a bit-line load circuit for rapid precharging of the bit line and a high-speed wired-OR column-sensing circuit.