A 10-B 20-MSAMPLE S LOW-POWER CMOS ADC

A single-ended input but internally differential 10 b, 20 Msample/s pi pelined analog-to-digital converter (ADC) is demonstrated with 4 mW pe r stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unsealed pipelined stages consu mes 50 mW including power consumed by a bias generator and two interna l buffer amplifiers driving common-mode bias lines, Key circuits devel oped for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-fol lower buffered op amp that achieves wide bandwidth using large input d evices, and a self-biased cascode biasing circuit that tracks power su pply variation, The ADC implemented using a double-poly 1.2 mu m CMOS technology exhibits a DNL of +/-0.65 LSB and a SNDR of 54 dB while sam pling at 20 MHz, The chip die area is 13 mm(2).