RESISTIVE INTERPOLATION BIASING - A TECHNIQUE FOR COMPENSATING LINEARVARIATION IN AN ARRAY OF MOS CURRENT SOURCES

A new technique called resistive interpolation biasing for accurately biasing a large number of analog cells on a VLSI chip is presented, Va riations in oxide thickness, mobility, doping concentration, etc., cau se inaccuracies in current ratios of two identically biased transistor s if they are placed sufficiently far apart on a chip, The proposed te chnique compensates for these inaccuracies without using any sampling or switching, The technique has been verified using a 2 mu m n-well CM OS process, Measurements show a factor of 3 improvement in terms of cu rrent ratio accuracy when the resistive interpolation technique is use d, The circuit can be implemented with a small chip area and low power dissipation, This technique finds applications where extensive curren t duplication over a large area is required (e.g., analog memories, D/ A converters, continuous-time filters, imaging arrays, neural networks , and fuzzy logic systems).