PRECISE FINAL-STATE DETERMINATION OF MISMATCHED CMOS LATCHES

The effect on the metastability of mismatched FET parameters and load capacitances of CMOS latch/flip-flop is analyzed. Theoretical analysis based on small signal devices are provided. From this study we show t hat the final state depends on both initial voltages and latch mismatc hes. A novel method using state diagrams is proposed. On the state dia grams obtained by transient analysis of the latch, a straight line can be approximately drawn that defines two semi-planes. This straight li ne (the metastable line) determines precisely the final latch state, a nd gives a very good insight about the mismatches which exist in the l atch. Several SPICE simulation results are shown for matched/mismatche d flip-flops. They agree well with the theoretical ones.