A 100-MHZ 2-D 8X8 DCT IDCT PROCESSOR FOR HDTV APPLICATIONS/

This paper discusses the design of a combined DCT/IDCT CMOS integrated circuit for real time processing of HDTV signals. The processor opera tes on 8 x 8 blocks, Inputs include the blocked pixels that are scanne d one pixel at a time, and external control signals that control the f orward or inverse modes of operation, Input pixels have a precision of 9-b for the DCT and 12-b for the IDCT, The layout has been generated with a 0.8 mu m CMOS library using the Mentor Graphics GDT tools and m easures under 10 mm(2). Critical path simulation indicates a maximum i nput sample rate of 100 MHz.