PITTING OF THE SILICON LAYER OF POLY BUFFERED LOCOS STACK

The poly buffered LOGOS (PBL) technology makes use of a thin silicon f ilm between a thermal silicon oxide layer and a silicon nitride layer. Pits or holes in the silicon film, formed in subsequent process steps , damage the underlying silicon and defeat the device isolation. In th is paper we study the influence of deposition temperature, and post-tr eatment on pit formation in LPCVD silicon films formed from silane and disilane precursors. We show that homogeneously amorphous silicon fil ms (deposition temperature much less than 550 degrees C) do not develo p device level pits during subsequent processing, in PBL technology.