TESTABILITY IMPLICATIONS OF PERFORMANCE-DRIVEN LOGIC SYNTHESIS

Retiming improves performance but also increases test generation time and decreases fault coverage. Research conducted at Carnegie Mellon an d McGill Universities attempts to explain the impact of retiming on th e testability of sequential logic circuits. A novel test preservation theorem suggests a powerful way to decrease the test generation cost o f retimed circuits. The authors also discuss a recently recognized cir cuit attribute that better explains the complexity of structural, sequ ential automatic test pattern generation.