LARGE-SIGNAL SUBTHRESHOLD CMOS TRANSCONDUCTANCE AMPLIFIER

A folding architecture for a subthreshold CMOS transconductance amplif ier is described in the Letter. Good linearity is obtained for an extr emely large differential input voltage, without loss in the common-mod e voltage range. Theoretical noise analysis indicates a 6dB improvemen t in the dynamic range compared to a simple single-pair MOS implementa tion. A prototype has been fabricated in a 2 mu m CMOS process, and ex perimental results are presented.