MECHANICAL AND ELECTRICAL EVALUATION OF A BUMPED-SUBSTRATE DIE-LEVEL BURN-IN CARRIER

A high-yield die supply has been identified as a key requirement for t he viability of commercial multichip modules (MCM). The result of die or wafer level test and burn-in (beyond the level of historical wafer probe) to provide dice with performance and reliability levels equival ent to single chip packaged (SCP) dice is commonly called known good d ie (KGD), There are many proposed methods to obtain KGD, at varying le vels of maturity, and with varying levels of cost, complexity, and pot ential impact on device performance and reliability, In this paper, we describe the mechanical and electrical evaluation of a temporary die- level burn-in carrier designed for use in providing KGD, Three device types are used in this evaluation to explore the limitations of the ca rrier system under evaluation: a 1 M DRAM, a 128 k x 8 SRAM, and a 56- k gate ASIC, Die size, and bond pad count, size and pitch all impact t he applicability of the carrier system under evaluation. Mechanical ev aluations performed to date include measurements of critical carrier f eatures such as bump height, die alignment structure placement, and bo nd pad damage caused by the carrier contacts. Electrical evaluations i nclude continuity and electrical test performance at multiple temperat ures.