PERFORMANCE, WIREABILITY, AND COOLING TRADEOFFS FOR PLANAR AND 3-D PACKAGING ARCHITECTURES

Citation
G. George et Jp. Krusius, PERFORMANCE, WIREABILITY, AND COOLING TRADEOFFS FOR PLANAR AND 3-D PACKAGING ARCHITECTURES, IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging, 18(2), 1995, pp. 339-345
Citations number
11
Categorie Soggetti
Engineering, Eletrical & Electronic","Engineering, Manufacturing","Material Science
ISSN journal
10709894
Volume
18
Issue
2
Year of publication
1995
Pages
339 - 345
Database
ISI
SICI code
1070-9894(1995)18:2<339:PWACTF>2.0.ZU;2-Y
Abstract
Models for wiring length, cooling, wireability, and signal distributio n are derived and integrated into a system-level performance metric us ed to compare packaging architectures for digital electronic systems. These include the common planar and stack-of-plane structures, in addi tion to fully 3-D structures with variable aspect ratios. This perform ance metric has been used to examine optimum packaging architectures f or air and water-cooled systems as a function of a number of parameter s including the total circuit count, The results show that none of the se packaging architectures is always optimal. Rather, the optimum stru cture is determined by the specific set of system conditions chosen. T he reader may easily use this model in order to determine the ''best'' packaging architecture for system parameters not included in this pap er.