PERTURB AND SIMPLIFY - MULTILEVEL BOOLEAN NETWORK OPTIMIZER

In this paper, we present logic optimization techniques for multilevel combinational networks, Our techniques apply a sequence of perturbati ons which result in simplification of the circuit. The perturbation an d simplification is achieved through wires/gates addition and removal which are guided by the Automatic Test Pattern Generation (ATPG) based reasoning. The main operations of our approaches are incremental tran sformations of the circuit (such as adding wires/gates and changing ga te's functionality) to remove some particular wire. At each iteration, a summary information of such wires/gates addition and removal is pre computed first. Then, a transformation is chosen to remove several wir es at once, We have performed experiments on MCNC benchmarks and compa red the results to those of misII and RAMBO. Experimental results are very encouraging.