NEW PERFORMANCE-DRIVEN FPGA ROUTING ALGORITHMS

Motivated by the goal of increasing the performance of FPGA-based desi gns, we propose new Steiner and arborescence FPGA routing algorithms. Our Steiner tree constructions significantly outperform the best known ones and have provably good performance bounds. Our arborescence heur istics produce routing solutions with optimal source-sink pathlengths, and with wirelength on par with the best existing Steiner tree heuris tics, We have incorporated these algorithms into an actual FPGA router , which routed a number of industrial circuits using channel width con siderably smaller than is achievable by previous routers. Our routing results for both the 3000 and 4000-series Xilinx parts are currently t he best known in the literature.