FAULT-TOLERANT FEATURES IN THE HAL MEMORY MANAGEMENT UNIT

This paper describes fault-tolerant and error detection features in Ha L's memory management unit (MMU). The proposed fault-tolerant features allow recovery from transient errors in the MMU. It is shown that the se features were natural choices considering the architectural and imp lementation constraints in the MMU's design environment. Three concurr ent error detection and correction methods employed in address transla tion and coherence tables in the MMU are described. Virtually-indexed and virtually-tagged cache architecture is exploited to provide an alm ost fault-secure hardware coherence mechanism in the MMU, with very sm all performance overhead (less than 0.01% in the instruction throughpu t). Low overhead linear polynomial codes have been chosen in these des igns to minimize both the hardware and software instrumentation impact .