ON FAULT SIMULATION FOR SYNCHRONOUS SEQUENTIAL-CIRCUITS

We investigate the considerations to be employed in designing a fault simulator for synchronous sequential circuits described at the gate-le vel. Three testing strategies and three methods of handling unknown st ate variable values are considered. Every combination of a test strate gy and a method of handling unknown state variable values defines a di fferent fault simulation procedure. Experimental results are presented to demonstrate the different fault coverage levels achievable by the various procedures. Based on these results, a fault simulation procedu re that combines the various considerations is proposed.