Rc. Taft et Jd. Hayden, A SCALED, HIGH-PERFORMANCE (4.5-FJ) BIPOLAR DEVICE IN A 0.35-MU-M HIGH-DENSITY BICMOS SRAM TECHNOLOGY, IEEE electron device letters, 16(3), 1995, pp. 88-90
We present the performance improvements obtained both by scaling the S
electively Compensated Collector (SCC) BJT and by using a modified Cur
rent-Mode Logic (CML) gate configuration. Scaling the perimeter parasi
tics by using the (tighter) bitcell design rules results in a approxim
ately 30% reduction in parasitic capacitances, and a 23% lower power-d
elay product; reducing it from 48 fJ to 37 fJ. The greatest return com
es from using a modified CML gate, which has an n-MOS current source.
At a supply voltage of 1.1 V, and at 40 muA switching current, the min
imum power-delay product of this CML gate is a silicon-substrate bipol
ar record 4.5 fJ.