REDUCTION OF THRESHOLD VOLTAGE SENSITIVITY IN SOI MOSFETS

The threshold voltage sensitivity of fully depleted SOI MOSFET's to va riations in SOI silicon film thickness was examined through both simul ation and device experiments. The concept of designing the channel V(t h) implant to achieve a constant dose within the film, rather than a c onstant doping concentration, was studied for a given range of film th icknesses. Minimizing the variation in retained dose reduced the thres hold voltage sensitivity to film thickness for the range of t(si) exam ined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The exper imental results confirmed the simulation findings and achieved a reduc ed threshold voltage sensitivity.