Yh. Jeong et al., ENHANCEMENT-MODE INP MISFETS WITH SULFIDE PASSIVATION AND PHOTO-CVD GROWN P3N5 GATE INSULATORS, IEEE electron device letters, 16(3), 1995, pp. 109-111
High performance enhancement mode InP MISFET's have been successfully
fabricated by using the sulfide passivation for lower interface states
and with photo-CVD grown P3N5 film used as gate insulator. The MISFET
's thus fabricated exhibited excellent pinch-off behavior with essenti
ally no hysteresis. Furthermore the device showed a superior stability
of drain current. Specifically under the gate bias of 2 V for 10(4) s
econds the room temperature drain current was shown to reduce from the
initial value merely by 2.9% at the drain voltage of 4 V. The effecti
ve electron mobility and extrinsic transconductance are found to be ab
out 2300 cm2/V.s and 2.7 mS/mm, respectively. The capacitance-voltage
characteristics of the sulfide passivated InP MIS diodes show little h
ysteresis and the minimum density of interface trap states as low as 2
.6 x 10(10)/cm2 . eV has been attained.