PARALLEL SIMULATION OF ATM SWITCHES

A simulation based approach to the problem of performance evaluation o f large switching fabrics is presented. Experimental results in the fo rm of cell queuing and buffer occupancy distributions for switches wit h up to 2048 inputs and outputs operating under a wide variety of load s are presented. The traditional dilemma between simulation model vali dity and its run-time where a more general purpose model inevitably re sults in longer run-times, is eliminated by the introduction of a new parameter: the architecture of the simulation platform. With model val idity as an invariant, the simulation platform can range from a sequen tial computer via shared memory and distributed memory general purpose parallel processors up to a dedicated emulator. An analytical model o f the class of applications under study gives insight in the influence of machine and problem parameters on simulator run-time performance. Examples of its use for the choice of an optimal parallel architecture for a given problem and of its use for the estimation of application behavior on a given parallel machine architecture are presented.