We report on the design considerations of stationary-head multi-track
magnetic recorders. We will focus on the particular reasons for adopti
ng the rate 8/10, dc-free recording code, the full-response detection
method, and the clock recovery circuitry. Implementation issues of the
channel chip, particularly related to cost and power consumption, wil
l be addressed. A new multi-track Phase-Lock Loop (PLL) was developed,
in order to improve the recorder's robustness against time-base varia
tions.