DESIGN, PERFORMANCE, AND EXTENSIONS OF THE RAM-DFE ARCHITECTURE

The design and performance of an adaptive RAM-Decision feedback equali zer integrated circuit (RAM-DFE IC) for magnetic recording channels is presented. The .8mum BiCMOS digital chip has been integrated with dis crete analog components in a 54 Mbps read channel. Description of the IC implementation details techniques to reduce latency and outlines tr adeoffs between performance and complexity. In an effort to achieve hi gher throughput, alternative decision feedback loop architectures base d on look-ahead computation are evaluated. A hybrid RAM/linear archite cture is found to approach 150 Mbps throughput with implementational a dvantages over both RAM and linear feedback filters.