MINIMIZING FPGA INTERCONNECT DELAYS

Authors
BROWN S KHELLAH M VRANESIC Z
Citation
S. Brown et al., MINIMIZING FPGA INTERCONNECT DELAYS, IEEE design & test of computers, 13(4), 1996, pp. 16-23
Citations number
11
Categorie Soggetti
Computer Sciences","Computer Science Hardware & Architecture
Journal title
IEEE design & test of computers → ACNP
ISSN journal
07407475
Volume
13
Issue
4
Year of publication
1996
Pages
16 - 23
Database
ISI
SICI code
0740-7475(1996)13:4<16:MFID>2.0.ZU;2-P
Abstract
Optimizing FPGA routing architectures for speed performance also invol ves improving the CAD tools for mapping circuits. Although their resul ts are sensitive to the tools used, the authors draw several basic con clusions about both FPGA routing architectures and CAD tools.