AN 85-MW, B-10, 40 M-SAMPLE S CMOS PARALLEL-PIPELINED ADC/

The design of a low-power 10 b, 40 Msample/s ADC integrated in a 0.8 m u m multithreshold CMOS process is presented, The fully differential d esign employs parallel-pipelined ADC each using a combination of singl e- and multibit-per-stage pipelined architectures, The ADC, targeted f ar high-resolution video terminals and ultrasound scanning application s, achieves a nonlinearity-plus-quantization-error of +/- LSB at 10 b, dissipates 85 mW from a single 2.7 V supply, and occupies an area of 1.9 mm by 2.1 mm.