ARCHITECTURE AND CIRCUIT-DESIGN OF A 6-GOPS SIGNAL PROCESSOR FOR QAM DEMODULATOR APPLICATIONS

A QAM processor for applications in QAM demodulators with baud rates o f up to 60 Mbaud and modulation schemes of up to 1024 QAM has been imp lemented on a single chip, The chip performs Ii-tap complex-valued ada ptive time-domain equalization and the complete digital base-band sign al processing of high-capacity QAM demodulators. This includes frequen cy-domain slope equalization and the digital parts of the timing and c arrier recovery as well as the gain and offset control for the A-to-D converters. The equalizer can be operated in baud spaced and half-baud spaced mode and can also be applied for cross-polarization interferen ce cancellation. The computational power of the QAM processor exceeds 6 giga-multiply-accumulate operations per second. Fabricated in an 1.0 -mu m CMOS technology on a silicon area of 185 mm(2) this 800 K-transi stor chip demonstrates the potential of such low-cost technologies. Th e maximum clock frequency under worst-case conditions is 60 MHz, The c orresponding power dissipation is 4.2 W.