We describe a set of placement algorithms for handling substrate-coupl
ed switching noise, A typical mixed-signal IC has both sensitive analo
g and noisy digital circuits, and the common substrate parasitically c
ouples digital switching transients into the sensitive analog regions
of the chip, To preserve the integrity of sensitive analog signals, it
is thus necessary to electrically isolate the analog and digital, We
argue that optimal area utilization requires such isolation be designe
d into the system during first-cut chip-level placement. We present al
gorithms that incorporate commonly used isolation techniques within an
automatic placement framework, Our substrate-noise evaluation mechani
sm uses a simplified substrate model and simple electrical representat
ions for the noisy digital macrocells, The digital/analog interactions
determined through these models are incorporated into a simulated ann
ealing macrocell placement framework, Automatic placement results indi
cate these substrate-aware algorithms allow efficient mixed-signal pla
cement optimization.